MZZ-HVS: Multiple sleep modes zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits,”IEEE Trans

Abstract—Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache leakage. In addition, as technology mi-grates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to reduce leakage in SRAM peripherals by putting them into low-leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an inte-grated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide leakage control mechanism and switch peripheral circuit’s power mode. The results show leakage reduction by up to 40 in deeply pipelined SRAM peripheral circuits, with small area over-head and small additional delay. This noticeable leakage reduc-tion translates to up to 85 % overall leakage reduction in on-chip memories. Index Terms—Horizontal and vertical sleep transistor sharing, leakage power, multiple sleep modes, SRAM peripheral. I